The present invention relates to the provision of test signals to electronic circuit components in a burn-in system and, in particular, to a system for generating test signals which contains a timing arrangement that eliminates any glitches in the test signals sent to electronic circuit components.
In a burn-in system, it is necessary to be able to selectably provide a variety of test signals in various sequences to the electronic circuit components under test. A problem with providing such test signals occurs when the input signals from which the test signal is chosen do not change state at exactly the same time. When this occurs, a momentary selection of the previous value of one of the input signals may occur. Such an inaccurate selection can manifest itself in the form of a glitch in the test signal. Such a glitch can adversely affect the operation of the electronic circuit components under test.
In some burn-in systems, glitches in the test signal are ignored. This can result in parts of the electronic circuit components being falsely triggered, interfering with their operation. In other burn-in systems, glitches in the test signal are minimized by limiting the order and variety of the test signals used so that a glitch will not appear. However, this solution limits the versatility of the burn-in system.
There is therefore the need for a system for generating test signals that is capable of providing a glitchless test signal to the electronic circuit components under test.